1. Field of the Invention
The present invention relates to a data processing apparatus which is embodied on-chip. More particularly, this invention relates to the initialization of such an on-chip data processing apparatus.
2. Description of the Prior Art
It is common for a data processing apparatus to be embodied on-chip, i.e. fabricated as an integrated circuit on a silicon chip. When such a data processing apparatus is started up, it is known for an initialization procedure to be carried out which is dependent on a reliable and stable clock signal being provided. For example, one way of carrying out the initialization procedure is under the control of a finite state machine (FSM) which leads the data processing apparatus through a well-defined set of states to ensure that the data processing apparatus is correctly configured for its subsequent data processing operations.
An on-chip clock signal can be generated by means of phase lock loop circuitry, which takes a supply voltage and generates a phase locked clock signal, which may either be used directly as the clock signal for the data processing apparatus or may be used to generate a system clock (for example by suitable gating of the phase locked clock signal). Because of the critical nature of the clock signal for reliable initialization, it is known for the initialization procedure for the data processing apparatus to hold the components which are to be initialized in a reset state until the phase lock loop circuitry indicates that the phase locked clock signal has been established. Only thereafter is the initialization procedure carried out (for example under the control of the FSM).
Accordingly, the level of the supply voltage provided to the phase lock loop circuitry is a critical parameter for reliably establishing the phase locked clock signal, in particular because the frequency at which the phase lock loop circuitry is able to generate the clock signal is dependent on the supply voltage level. Phase lock loop circuitry is typically able to accept a modest variation in the supply voltage and to still be able to generate a target frequency for the phase locked clock signal. However if the variation in the supply voltage level is too great, then the phase lock loop circuitry may be unable to establish the phase locked clock signal at its target frequency.
However it may also be the case that in order to function correctly, the data processing apparatus must be able to operate using a range of supply voltages which exceeds the variation which the phase lock loop circuitry can tolerate in order to establish the phase locked clock signal. One such example of this may arise in the context of an on-chip data processing apparatus which is required to communicate with an off-chip destination according to a given data exchange protocol. For example, where the data processing apparatus is a DDR PHY component of a System-on-Chip (SoC), the DDR PHY component may be configured to communicate according to a number of JEDEC DDR protocols (e.g. DDR, DDR2, DDR3 and the various different standards defined for each). Each JEDEC DDR protocol has a defined operating voltage and data transmission frequency and the DDR PHY component must be configured to operate using the corresponding operating voltage and at the corresponding data transmission frequency. Whilst a particular DDR PHY component could be configured to be used only for one particular DDR protocol, it is clearly advantageous if a generic DDR PHY component can be provided which is able to operate in accordance with as many DDR protocols as possible.
However the above mentioned limited tolerance of the phase lock loop circuitry can be a limiting factor on the ability of a system designer to provide such an “all purpose” data processing apparatus, which is required to cope with both a range of operating frequencies and supply voltages. Indeed the interplay between the supply voltage level and the frequency at which the phase lock loop circuitry is able to establish a phase locked clock signal can result in a deadlock situation when trying to initialize such a data processing apparatus, in which it is not possible to establish a phase locked clock signal at a particular frequency due to the supply voltage not being compatible with phase locking at that particular frequency. This leads to the requirement to determine the level of the supply voltage before determining a target frequency at which phase locking the clock signal is possible.
A known method for determining the level of the supply voltage involves the use of bandgap circuitry to provide a very precise reference voltage against which the level of the supply voltage can be compared. However, whilst a reference voltage can be provided very precisely by bandgap circuitry, its operation is very process dependent (thus needing silicon correlations) and it is typically both large (in terms of silicon area) and power hungry.
Accordingly it would be desirable to provide an improved technique for enabling the above-mentioned phase locking of the clock signal and apparatus initialisation.